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Investigating Flash memory wear levelling and execution modes

Soraya Zertal, Peter G. Harrison

Journal Article
SIMULATION
Volume 87
Issue 12
pp.1081–1091
December, 2011
Sage Publications, Inc.
DOI 10.1177/0037549711417187
Abstract

The impact of wear levelling on a Flash storage package and its access operations' execution modes is investigated. First, a simple, static logical-to-physical mapping function is proposed and its implied wear levelling is assessed for different distributions of addresses, covering both uniform access and hotspots, as well as the Flash chip utilization within the whole package. Second, for each access mode, different preemptive and non-preemptive priority schemes are considered with a range of IO arrival rates, using Poisson-, Erlang- and Pareto-based arrival processes. The analysis of the impact of the execution modes on the performance of the Flash memory is undertaken using a hardware simulator. The results show clearly the good wear levelling obtained by the mapping functions, even in the presence of hotspots. In addition, the impact of the chosen execution mode on the whole storage package for each IO workload type is assessed, both qualitatively and quantitatively.

Notes

An earlier version of this paper was presented at the 2009 International Symposium on Performance Evaluation of Computer & Telecommunication Systems (SPECTS 2009) and is available online at http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5224140

Information from pubs.doc.ic.ac.uk/flash-memory-wear.