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Modelling and validation of shared memory coherency protocols

Andrew Bennett, A. J. Field, Peter G. Harrison

Journal Article
Performance Evaluation
Volume 27
pp.541–563
September, 1996
Elsevier
DOI 10.1016/S0166-5316(96)90045-0
Abstract

We present an analytical model of a cache coherent shared-memory multiprocessor and compare the results obtained with those from an execution-driven simulation of the same system.

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Information from pubs.doc.ic.ac.uk/perf96.